1. Field
The following description relates to a semiconductor device, and to a semiconductor device configured to suppress an electric field that is formed around an edge of a gate pad of a semiconductor device of Trench Termination structure.
2. Description of Related Art
According to recent large-scale, large-capacity trend regarding all sorts of electric/electronic devices, there is a need for a device having characteristics of a high breakdown voltage, high current, and high speed switching. It is desirous for semiconductor devices to have such characteristic of high breakdown voltage to endure a reverse direction high voltage of P-N junction that is applied to both ends of the semiconductor device, in an off state or at the moment when a switch is turned off. A low on-resistance or low saturation voltage is desired so that a very large scale current may flow and power dissipation may also be small under a conductive state.
Researches and developments have been undertaken regarding semiconductor devices that have the aforesaid technical characteristics. FIGS. 1 to 3 show examples of such semiconductor devices.
FIG. 1 is a plan view of a semiconductor device having an active area and a termination area in accordance with the conventional art. FIG. 2 is a partially enlarged plan view of a part in FIG. 1. FIGS. 3A to 3C are cross-sectional views taken along lines I-I′, II-II′, and III-III′ of the semiconductor device shown in FIG. 2.
As shown in FIG. 1, a semiconductor device 1 includes a gate pad 10, an active area 20 that comprises multiple trenches 21, 22; a termination area 30 that surrounds the active area 20; an isolation area 40 that isolates the active area 20 and the termination area 30. The active area 20 indicates an area in which a semiconductor device operates and a current flows. The isolation area 40 is formed in a trench structure, partitioning an active area 20 and a termination area 30.
A semiconductor device configured as shown in FIG. 1 is desired to have a low drain-source on resistance (RDSon). The RDSon is a drain-source resistance at a specific drain current and gate source voltage. To this end, by forming an oxide layer (i.e., SAC2 Ox, RESURF Ox, Field Ox) to an inside of trenches 21, 22, which are formed in the active area 20, an electric field is supported between trenches.
However, because a space between the trenches cannot be regularly maintained in some areas, an electric field cannot be stably supported. This will be described with reference to cross-sectional views shown in FIGS. 2 and 3A to 3C.
FIGS. 3A to 3C are diagrams illustrating examples of cross-sectional views taken along lines I-I′, II-II′, and III-III′ in the partially enlarged view of FIG. 2.
One or more trenches 21, 22 are formed in an N-type substrate 50, and an oxide layer 54 is formed to the inside of the trenches 21, 22. The trench 21 is a Triple Poly Structure where one center poly electrode 56 and two gate poly electrodes 58 are formed. A P-body area 60, 60′ is formed in an upper area of the trench 21 side; an N+ source area 62 is formed through an N+ dopant ion implantation in the P-body area 60 among them.
An oxide layer 70 and an extended gate poly electrode 72 are formed on the N-type substrate 50 and an ILD (Inter Layer Dielectric) 74 is formed on the extended gate poly electrode 72. Multiple via holes 75 are formed in the Inter Layer Dielectric 74. A source metal 76 that is formed on a partial area of the Inter Layer Dielectric 74 is able to contact the center poly electrode 56 and P-body area 60′. A protective layer 78 is formed on the Inter Layer Dielectric 74 and the source metal 76.
In the figures showing a cross-sectional view of FIG. 2, referring to FIGS. 3A and 3C, a space between trenches is regularly maintained, thus, stably supporting an electric field between trenches. An area of II-II′ in FIGS. 2 and 3B, there is no trench formed around an edge of a gate pad 10, i.e., a space between the trenches is not regular so that a gate electrode and a source electrode may be isolated. Accordingly, at a point ‘a’ of FIG. 2, a drain-source leakage current (IDSS) increases.
FIG. 4 is a diagram illustrating an example of a measurement graph of drain-source leakage current (IDSS) in a semiconductor device having a structure of FIG. 2. Referring to FIG. 4, it may be understood that a drain current (ID) drastically increases at a specific point when a drain-source voltage increases. When this happens, a semiconductor device cannot secure against a high drain-source breakdown voltage (BVDSS), thus subsequently causing efficiency of the semiconductor device to be degraded.